With backplane finished, next step is to design a number of modules that plug into it. It would be the same as the old FAP, consisting of CPU board, memory board, video card, and I/O board. In this post I’ll get the first three out of the way, since they are have not changed much.
And because they are still largely the same, albeit laid out nicely on a PCB, I’m not going into details about how they work in this article, check out the older entries for those details.
One thing that did change was the bus voltage. Originally the bus runs at 5V since both Z80 and memory operates on that voltage. However, the FPGA video card only tolerates 3.3V, so was the CPLD that I’m planning to use for the I/O board. So in the spirit of doing things properly, the new FAP’s bus will be running on 3.3V. How are we going to achieve that? Take a look at Z80’s data sheet:
Looks like inputs are at TTL level, meaning they only needs 2.2V to be registered as high, so 3.3V inputs should work. However, for some reason clock inputs still needs at least 4.4V, so that will need level translation. To shift signal level up, power the 74 chip at 5V and give it the input at 3.3V, buffered 5V signal will come out the other end. Similarly, to shift down power the chip at 3.3V and give it 5V inputs, 3.3V signal will appear on the output.
As before I used 5 74HC245 bidirectional bus transceiver as both level translator and buffer. Every single signal is broken out on the bus, buffered, and all at 3.3V. The jumper wire you see on the picture below is to correct a small error in the first revision of the PCB, the latest board file in the project GitHub already had it fixed.
CPU Control inputs such as CLK, INT, NMI, WAIT, BUSREQ, RESET needs to be pulled up as they need to be at defined state at all times. I also added LEDs for power and BUSACK. Decoupling capacitors are used liberally, since I was in so much trouble with noise last time.
Next up is memory board. I’m actually planning to design a memory board with a modern flash memory for both ROM and RAM, and a CPLD as memory controller, but for now I’m sticking to the old plan: 32KB ROM from 0x0000 to 0x7fff, and 16KB RAM from 0xC000 to 0xffff. The missing 16KB at 0x8000 is used for VRAM.
In the old FAP I piggybacked two memory chips so it needed less wiring, this time I again did it properly and put them side by side. Those two chips runs at 5V but takes 3.3V inputs as well, so only one output buffer-shifter is needed. I also changed the the write enable signal of the EEPROM by ORing it with BUSACK, so that EEPROM write is only possible when CPU is off the bus, that means misbehaving programs will not be able to write into ROM during normal execution. Another couple of LEDs round up the board.
Funny thing happened when I tested the newly assembled memory board, as writing into addresses beyond 0x2000 will change the data starting in 0x0000, I thought there was some short in the address line, but in the end it turned out my eBay-bought AT28C256 32KB EEPROM chip is a fake, and it’s actually a AT28C64 8KB part. They actually spent the effort sanding off the original marking and laser engraved a new one. I ordered some more from mouser, and I guess I’ll have to make do with 8KB for now, which is still plenty.
Next up: video card
This one is pretty straightforwards as well, I’m still using the Mojo V3 FPGA board piggybacking on the circuit board, and two SRAM chips for double buffered video memory. 6-bit R-2R DAC produces 64 colors, and a nice VGA connector instead of just wires.
Being the board with the highest speed signals, 25MHz pixel clock, the improvement in video quality is night and day compared to the old hand-wired board. The whole display is much sharper than before, and ghosting and color desync is gone.
There are still some issues though, in the rush to get the board made I didn’t realise the VGA connector actually blocked the USB port on the Mojo, so I had to either take the Mojo off to program it or remove the VGA connector, I did the latter. This has been fixed in the project repo. The other thing was I ran out of pins on the Mojo, so I had to omit some signals that I would otherwise like to include for more functionality. I saved 2 pins on the VRAM address line, halving VRAM from 32KB to 16KB, I also had to give up the maskable interrupt interface and use NMI instead. When I have time I’m going to design FAP’s video card with on-board FPGA instead of using Mojo, but for now it it’s still pretty capable.
With the boring stuff finally out of the way. I/O board is next, and it’s going to be a long one.