Memories of FAP

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Now that FAP’s Z80 is free running with hardwired NOP, the next step would be to add some memories so I can store programs into it and thus executed by the CPU. So in this part of the build log I’m going to add some ROM and RAM to my computer.

I purchased a couple of AT28C256 EEPROM as well as HM62256 Static RAM. Both are 32KB chips in DIP, and fairly often used in homebrew computer builds. But before that, some housekeeping to do. Since I’m going to make another card with both memories on it, I need to add another slot on the backplane. And because the backplace strips are 5-wide, which is too close to put another card right next to the CPU card, I bridged it with male double row headers and some jumpers.

 

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From top to bottom: CPU card, bridge, memory card slot.

Now comes the difficult part, before I start building I need to plan out the memory map of FAP, only when that is done can I start designing memory decoding logic and all the rest of it. After some reading I decided to keep it simple, and the memory map of FAP will be like this: 16KB ROM from address 0x0 to 0x3FFF, and 16KB RAM from 0x4000 to 0x7FFF. Since Z80 can address 64KB of memory directly, that leaves me with 32KB of unmapped memory, which can use for VRAM or some other memory mapped IO device. I guess 16KB is of RAM and ROM is plenty for now, if I needed more I can make another card.

Now comes the memory decoding, I’m going to use address lines for chip select signal, and MREQ’, RD’ and WR’ for OE’ and WE’.  For chip select, notice how the most significant two bit of address select the memory. When both A15 and A14 are 0, address are within 0x0000 and 0x3FFF, which selects the ROM. Since both A15 and A14 has to be low for CS’ on ROM chip to be low, it’s easy to see a simple OR gate is enough. Memoy read is enabled when both MREQ’ and RD’ are low, again, OR gate. Memory write is exactly the same, active when both MREQ’ and WR’ are low, another OR gate. 3 OR gates, perfect for one 74HC32, which I have. The CS’ and WE’ signals are shared between two chips. And since we’re using only half of the chip, A14 on each chip is tied to the ground.

Now for selecting RAM, its CS’ needs to be low when A15 is low and A14 is high, which means inverted A15 NAND A14, I can use a 74HC00 for that.

So, below is the schematic for FAP’s memory card, only 4 chips, not bad.

 

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FAP’s Memory Card

Now comes the question of how to program the EEPROM, fortunately it’s largely not a problem because I can just pull low the BUSREQ’, clock the CPU until BUSACK’ is low, this put the address, data and control lines into high-Z and kicks the CPU off the bus, then I just write to the EEPROM by driving the bus with the STM32 board. Which is much simpler than Veronica‘s solution with a dedicated programmer and bus arbitration switches. Everything is done in the STM32F1 board, which is the big advantage I talked about in my first post.

Time to build the board first on breadboard and test it, there’s not much to write about the building process, apart it consuming my entire collection of jumpers. I also put two LEDs on CS’ lines so I can see which chip is being selected. So does it work? Look at the video below.

In this demo I simply put some address on the bus in 0x1000 increments, you can see the ROM chip select’s LED lights up when address is bewteen 0x0 and 0x3FFF, and RAM’s LED lights up when address is between 0x4000 and 0x7fff.

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What a mess

Next up is trying to read or write some values into the ROM, it’s relatively slow to write to EEPROM, each byte may take up to 10ms, that means it’ll take a whopping 160 seconds to write 16KB into it. It does support page write mode that writes 64 bytes at the same time, but it’s not implemented for now.

As reading EEPROM is fast while writing is slow, I wrote my EEPROM write function to check the existing data first, if they’re the same a costly write can be skipped. In the video below I’m writing the first 256 bytes of the ROM with its address, as in writing 0x1 to address 0x1, 0x2 to address 0x2 etc. In the first pass you can see it’s writing into the EEPROM, the second pass the value is already the same so it’s skipping every single write.

So far so good. Things went a bit wrong when trying to write to SRAM though, the write seems to work, but when read back the data is close, but not exactly the same as what has been written to it. I thought it was the timing difference between the ROM and RAM write, after almost an hour of tinkering with the code to no avail,  I decided to check the connection and discovered that I wired two of SRAM’s address lines wrong. I should have known since it’s as you can see it’s such a mess.  After correcting the wiring, it worked like a charm, which means it’s time to go on the actual card.

Bit of soldering later, I put ROM and its decoding logic on the card.

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FAP memory card with just ROM and its decoding logic

Next step is RAM, however if you look at the datasheet, you’ll realize the pinout of the two chips are exactly the same, so instead of soldering another 28 wires I decide to simply piggyback the RAM on top of ROM, a technique Quinn also used in her Veronica.

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FAP’s super NSFW RAM on ROM action

By soldering every pin of the two chips together apart from the chip select, I can put the piggyback chips back in the socket and only hook up the cs line for the new RAM chip. Below is the completed memory card.

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Completed FAP Memory Module
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Piggybacked RAM with its CS signal

To test it, I loaded up ROM with 0 and let it ran, it was exactly the same as the free run last time, so I didn’t take a video, but it worked nevertheless!

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Now the my computer have its own memories, I can finally upload some program into it and let it actually do stuff. However, without any means of input or output, FAP is going to be a hard sell for anyone else. That would be my next step, maybe making a VGA video card, or a UART, or even reading a keyboard! Stay tuned to find out on the next episode of the Adventure of FAP!

As usual, you can find the up-to-date resources on the Github repo of this project.

Next Post: Programming FAP
Previous Post: Bus Board, CPU Board, and Freerunning FAP
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Bus Board, CPU Board, and Freerunning FAP

Project Github Repo

Previous Post: Long Time Coming: Building the FAP Z80 Computer

Next Post: Memories of FAP

Finally we’re going to to actually start building the computer! I’m probably going to rather frequently compare what I’m doing to  what Quinn Dunki did with Veronica, since a large part of this project’s inspiration comes from hers.

Let’s start from the very basics, the construction material. Quinn etches, drills and solders her own circuit board, I don’t have such luxury here so I’m going to make mine out of prototyping boards, first comes to mind is the perfboard, I already have a couple of them laying around and thought it’s a good idea to use them. As it turns out 3 hours later, no, just say no.

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Perfboard: not even once

If you don’t know about perfboard, it’s a regular PCB with drilled holes in a square grid of 0.1 inch spacing, and each hole is electrically isolated from each other, and that means you have to either wire wrap, which I don’t have, or use point to point soldering, which means soldering every single connections using 30AWG wires, which is hard to strip and position because they won’t stay in place. It’s alright for smaller projects, but if I did the whole thing using perfboard I might well be dead before even got to the F part of the FAP.

A bit of internet search later, I got some new prototyping boards that I’ll be using to build the computer, first of all is the large “motherboard” or “backplane” where all the modules will be plugged in. It’s a board with 5-hole conductive strips grouped together, so it’s sort of like a stripboard but not really. This board is around 6 x 8 inches, enough for a couple of expansions later on.

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This will be FAP’s backplane

 

Now we have the motherboard, next up is the boards that our modules use, for that I bought what some may call “solderable breadboards”, which is basically PCBs with breadboard patterns. This is much better than perfboard because you can use solder wires to the adjacent pins of components, and it already has power buses available. This board is 5.5 x 3.7 inch, perfect fit for plugging into the backplane vertically.

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FAP’s modules will go on this.

Now a little bit about bus design, Quinn uses ISA connectors for her Veronica with 31 pins available, it works when you make your own PCB, but obviously not here. So I’m going to go with the tried and true pin headers. Double row female pin headers on the backplane, double row right angle male pin headers on the modules, and it’ll plug right in. And because the two rows are connected on the module card, it will bridge the gap between 5-hole groups on the backplane as well. What’s more, pin header comes 40 pins wide, a nice number for a system bus, and I can add more later if I want.

With the basics done, it’s time to design the bus pinout and the CPU board. Because it’s my first time doing this, I’m going to play it safe and put almost all CPU signals onto the bus. Pin 1 will be 5V,  pin 2 to 9 is DATA[0:7], pin 10 to 25 is ADDRESS[0:15], pin 26 to 37 is every single CPU control signals apart from REFRESH and HALT, since we’re not using dynamic memories, pin 40 is GND. This leaves 2 pins free on the 40 pin bus, and have the option to make it even wider by just adding more pin headers, pretty good.

For the CPU board itself, it’s pretty straightforward. ADDRESS and DATA lines are buffered with 3 74HC245s, while control signals are connected to bus directly, if it turns out those needs buffering too I can add them later. Since ADDRESS is output only, the DIR pin on the ‘245 is tied to GND so B side is input. As for bidirectional DATA lines, I connected the DIR pin to WR’. When WR’ is active(low), DATA lines are output, and in 245 data goes from B to A, when WR’ is inactive(high), DATA lines are input, and 245 data goes from A to B. The output enable of the 245s are connected to inverted BUSACK’ signal, so when BUSACK’ is low, output enables are high, ADDR and DATA goes into high impedance, kicking the CPU off the bus. Below is the schematic.

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CPU board schematic

Time to start building. Here are all the chips in place with all the power connections, as well as the DATA line from the buffer to the header. I had to cut a single line off the bottom of the board so the male header actually sticks out.

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One hour later, all the connections are done, it looks like a mess, but that’s what happens with this many signals.

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Completed CPU board

Making sure there is no shorts between power buses and all the connection are correct with the continuity tester, the CPU board is done. The logical next thing to do it test it. It’s not as easy as it sounds though, the CPU needs clock signal, data inputs, and 6 control signals, and I need a way to see what’s on the ADDRESS and DATA bus to see what the CPU is doing, we need some way to do all those.

What Quinn did was designing a dedicated clock circuit with monostable 555 for single-step clock, as well as crystal oscillator for full speed clock, and SPDT switch to select between the two. And for visualizing the bus content, the HexOut display module. It’s fun and all designing all those support circuits, but I’m going to skip all that trouble and use a microcontroller to control the FAP in the early stage of the development. Since the microcontroller is programmable I can clock the CPU as fast or slow as I want, put anything I want on the DATA bus, see what’s on the ADDRESS bus, achieve reliable power-on resets, monitor and change all the control signals, and it also acts as a USB power supply. It’s much more robust and customizable than using dedicated circuits, takes much less space, and probably cheaper in the end too.

The microcontroller in question is the STM32F103VCT6 on its Minimum System Development Board from ebay. This little beast of a uC has 5 16-bit GPIO ports, a total of wooping 80 GPIO pins, plenty enough for FAP. It also has 256KB of flash memory and 64 KB of SRAM, which means I can fit the entire addressable space of Z80 inside the flash memory of this uC 4 times if I want. It also runs at 72MHz, 18 times faster than Z80, and has a million peripherals that I’m not going to use in this project. And the best thing about it is that it doesn’t have all the bullshit components tacked on like they do in the Discovery boards ST makes themselves, just a simple minimal working system with all the pin broken out, and nothing else. How much for this? $6.5. If not because of the extensive libraries, there is almost no reason left use Arduino now we have this. All in all, not bad at all.

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FAP’s brain, at least in the beginning.

I thought I would finish the backplane board before testing the CPU board. The blackplane is pretty simple too, all the bus signals goes into the microcontroller, a couple of buttons for reset and clock control, and two UARTs will be used, one for debug output, one for serial LCD. The entire PORTE will be used for ADDRESS, lower 8 bit of PORTD for DATA, PORTC for control signals, PORTB for buttons, and PORTA for 2 UARTS.

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The construction is similar to the CPU board, just tons of wires solder, which isn’t very interesting. I needed to cut across two traces so that the double row headers on the controller board doesn’t get connected together.

 

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Box cutter works

Finished backplane, the 40-pin double-row header is for CPU card, the controller goes to the lower right, and buttons are for reset, single step, and run/stop.

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Finished backplane board.

Well not actually quite finished, I forgot to add the two UART headers. I used a bluetooth module, so I don’t have to attach another wire to it. Here is the really finished board:

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Really finished backplane board.

Now it’s finally time to test the CPU board. We want the CPU to execute some instructions, but since we don’t actually have any memories, I’ll start with a simple one. What I’ll do is to tie the DATA line to GND, all the control inputs to VCC, hold RESET low for at least 3 clock cycles to properly reset it, then clock it normally. The CPU will start executing from address 0x0, and fetch an instruction from the DATA bus, it will be 0x0 since I tied all of them to GND. The Z80 will therefore execute the 0x0 instruction, which happens to be NOP, which doesn’t do anything at all. It will simply go to the next address and fetch another instruction, which is still 0x0, another NOP. In the end it just keeping going to the next addresses, and we can see the address increase in the ADDRESS bus, this is called free running the CPU, a simple way to make sure my CPU is working.

I set lower 8 bits of PORTD, which is connected to DATA bus, to output 0, and PORTE, connected to ADDRESS bus, as input. The content of ADDRESS and DATA bus are displayed on the LCD screen, and CPU are clocked by pressing a button, or set to run continuously at the press of another button.

Well does it work? See for yourself:

As you can see, I started by single stepping the clock, each time I press the button the clock advances 1 cycle. It takes 4 cycles for the address to advance 1, which is in line with what datasheet states.Capture

After letting it free run for a while, you might notice the address is fluctuating instead of simply going up. This is due to the memory refresh operations that is built into the Z80 so it would be easier to use with the cheaper DRAM. I stopped the clock to single step again, and you can see the address changes every two clock cycles now, just like the what datasheet say again. The first two cycle is PC, and the last two is refresh address.

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After thinking long and hard about the design, my FAP finally lives! All is well, I’m glad it works after all the work. Next step is to add some ROM and RAM, so it can actually execute some meaningful instructions. Stay tuned to find out more!

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FAP lives!

 

Again, you can find the up-to-date resources on the Github repo of this project.

 

Previous Post: Long Time Coming: Building the FAP Z80 Computer

Next Post: Memories of FAP

Long Time Coming: Building the FAP Z80 Computer

Next article: Bus Board, CPU Board, and Freerunning FAP

 

I figured that I should start documenting my ongoing projects here from now on. I guess it might help other people with similar interests, or maybe just myself so I don’t lose the details in a few years time.

Over the years I worked on a number of projects involving embedded systems, interesting stuff like the Gamecube controller mod for 3DS, a shiny finder for 3DS Pokemon games, custom hardwares for TwitchPlaysPokemon channel, and a whole bunch of others that I might write about later. Despite all these though, something has always been lingering at the back of my head. I wanted to build an entire computer from scratch.

Back in the late 70s and early 80s, the microcomputer market was dominated by two 8-bit processors, Zilog Z80 and MOS Technology 6502. Almost all popular personal computers of the era had one of these two chips, 6502 was used in the likes of Apple I, Apple IIe, Commodore PET, Commodore VIC-20 and BBC Micro,  while Z80 was used in Osborne 1, Radio Shack TRS-80, ZX Spectrum, Commodore 128, along with countless others. Those chips were powerful enough to do some real work, but also simple enough so one can design a fully featured computer by him/herself. And that’s why a large number of retro computer projects on the internet uses one of these two. Another major factor of those retro builds is the nostalgia, as many had their very first computer with those processors. My first computer was a Pentium III, so I guess that’s out of the window for me.

Or is it?

It turned out that those two chips were so popular, they were used in tons of video game consoles as well, 6502 was used, among others, in Atari 2600, 5200, 7800, NES, and Atari Lynx, while Z80 ended up in ColecoVision, Sega Master System, Game Gear, Genesis, SNK Neo-Geo, Nintendo GameBoy, Gameboy Color, Gameboy Advance, as well as classic arcade game machines like Pac-Man, Frogger and other Namco and Sega arcade systems. So if you like video games, you have 6502 and Z80 to thank for. I do, and that’s why I’m planning to build a retro machine out of one of these chips. Of course general propose computers are not exactly the same as game consoles. What I’m planning is to build a computer first, and then try to build a console clone once I got up to speed with designing retro computers.

Now comes the part of picking between the two, I choose Z80 because it has more registers, somewhat more powerful, and seen by some to be more of a “proper” microprocessor since 6502 was the “cheap alternative” back in the day. Actually I wouldn’t know since I never worked on a 6502 anyway. The real reason though, is that Z80 was used in Nintendo Gameboy lines, and that’s the one I grew up with. You see, it’s still all about the nostalgia.

As for the PC,  it’ll have the Z80, some RAM and ROM, a video card, and some kind of input like a joystick or keyboard. I might add or delete stuff along the way but I’ll start simple in the beginning. If you’re planning to build your own Z80 computer, one of the must-reads is the appropriately named Build Your Own Z80 Computer by Steve Ciarcia, in this 1981 book he explains step-by-step the process of building a Z80 computer from scratch, starting from the power supply, to adding RAM and ROM, and to advanced stuff like CRT terminal and tape drive interface. He calls his computer ZAP, which stands for Z80 Application Processor. In the similarly thoughtful and serious vein I’m going to call mine FAP, which is FPGA-Assisted Processor. Where is the FPGA you ask? Most likely for the video card. But it’s going to be a while for me to get there, so don’t worry about it right now.

One thing you’ll realize is there are going to be a lot of planning to do before you even start building anything, now that we have picked the processor and the rather excellent name, next is to decide the form factor of my FAP. At this point it’s impossible for me to not mention the biggest inspiration that made me, and probably a lot others, to pursue my project, Quinn Dunki’s Veronica computer. Running the Blondihacks blog, she documents a number of her projects in detail, stuff like repairing a pinball machine, fixing and hacking an Apple IIc computer, and most importantly in our case, the Veronica. The Veronica is a 6502-based computer she built from scratch just like what I about to do, she started from just freerunning the CPU, and ended up adding RAM, ROM, designing the GPU with VGA output, modifying a retro radio case to put it in, adding the gamepad input and USB keyboard interface, over the journey of 3 years.  Quinn chose not to build a Single Board Computer, instead going for a bused design, this way everything is modular, and it’s trivial to upgrade or add functions, just plug a new card in. I fully agree with this design direction, and FAP will be using the backplane design too, although there will be a few different details regarding the implementations which we shall see in later posts.

For now I think this introductory post is long enough, we’ll get into the meat of FAP starting from the next article where I’ll actually start building stuff.

Next article: Bus Board, CPU Board, and Freerunning FAP